One type of prior art volatile memory is the random access memory ("RAM"). A RAM typically includes a memory array for storing data. Data can be written into and then read from the memory array at addresses. No prior erasure is required to write new data into the memory array. FIG. 1 shows the structure of a prior art RAM 10.
As can be seen from FIG. 1, a column decoder and read/write select circuit 13 is connected to a memory array 11 via a column gating circuit 14. Circuit 13 selects a number of columns in memory array 11 via column gating circuit 14 for a memory read or write operation for each address received. A row decoder and select circuit 12 selects a row in memory array 11. Memory cells at intersections of the selected columns and row are selected cells. Circuit 13 also receives a read enable signal READ and a write enable WRITE signal. The READ signal causes the selected cells to undergo the read operation and the WRITE signal causes the selected cells to undergo the write operation. Data stored in the selected cells are sensed by a sense amplifier 16 during the read operation. Data to be written into the selected cells are applied from a data buffer 15 during the write operation. FIG. 2 shows the circuitry of column decoder and read/write select circuit 13 that includes a column decoder 21 and a read/write select circuit 22. FIG. 3 shows the array configuration of memory array 11 and column gating circuit 14.
As can be seen from FIGS. 2 and 3, during a write operation, the WRITE signal is asserted and the READ signal is deasserted. This causes all the read select outputs of circuit 22 not to be asserted. If a decoder 21a of column decoder 21 decodes a portion of a column address to select column COLUMN0 of memory array 11 by asserting a Y0 select signal, the Y0 select signal then passes through an AND gate 22b of circuit 22 to become a WRITE-Y0 signal. The WRITE-Y0 signal then causes gating transistor 32c to connect column line 30a to a NAND gate 15a and gating transistor 32d to connect column line 30b to a NAND gate 15b. Column lines 30a and 30b are a pair of complementary column lines for column COLUMN0. Depending on the data to be written, either line 30a or line 30b is brought to logical low state. NAND gates 15a and 15b apply the write data under the control of the WRITE signal. NAND gates 15a and 15b and inverter 15c are part of data buffer 15 of FIG. 1.
When the READ signal is asserted while the WRITE signal is deasserted, memory 50 then undergoes the read operation, the Y0 select signal then passes through a NAND gate 22a of circuit 22 to become a READ-Y0 select signal. The READ-Y0 select signal then causes gating transistors 32a and 32b of column gating circuit 14 to connect column lines 30a and 30b to sense amplifier 16a. Sense amplifier 16a then senses the data stored in the selected memory cell along column COLUMN0. Sense amplifier 16a is part of sense amplifier 16.
Disadvantages are, however, associated with this prior art memory shown in FIGS. 1 through 3. One disadvantage is that a memory cell may be accidentally written with a data bit left along a column of the memory from a prior write operation due to insufficient data recovery in the memory. As is known, in order to allow a memory to operate fast, each of the read and write operations of the memory needs to be switched off and the address of the operation needs to cease to be applied to the memory as soon as the operation ends such that another operation can immediately follow. However, if the address of a write operation stops being applied to the memory too quickly during the operation, the respective gating transistors of column gating circuit 14 may be switched off well before the write operation ends. This may allow insufficient time for the selected columns of the memory to recover the data and the data may still remain in the selected columns. When another memory read or write operation follows, the data remaining in the selected columns of the previous write operation may be accidentally written into memory cells located at the intersection of the selected columns of the previous write operation and the selected row of the current memory operation. For example, if a prior write operation is to write data into memory cell 31b, the WRITE-Y0 signal causes gating transistors 32c and 32d to conduct and the WRITE signal causes the write data to pass through NAND gates 15a and 15b, respectively, to be applied to the respective one of column lines 30a and 30b. Row decoder 12 (FIG. 1) then selects word line 35b. This causes the data applied at column lines 30a and 30b to be written into memory cell 31b. At the end of the write operation, the WRITE-Y0 signal is deasserted as soon as the address ceases to be applied to column decoder 21. This turns off gating transistors 32c and 32d, as seen in FIG. 4. As can be seen from FIG. 4, the WRITE signal is deasserted at timing t.sub.1. However, the WRITE-Y signal is deasserted at timing t.sub.0. The WRITE-Y signal of FIG. 4 represents any of the write column select signals WRITE-Y0 through WRITE-Ym from circuit 22. This causes the data recovery process of column lines 30a and 30b to be terminated before the write operation is terminated, which causes the data to remain in lines 30a and 30b at the end of the write operation. If, for example, a read operation to memory cell 31d immediately follows the write operation, the data remaining in column lines 30a and 30b may be accidentally written into memory cell 31a when row decoder 12 selects word line 35a to read memory cell 31d along column lines 30c and 30d.